Field of the Invention
The invention relates to a method for fabricating an integrated semiconductor circuit, in which a computer program is used to compute a circuit diagram, and a semiconductor circuit is fabricated on the basis of the circuit diagram. The circuit diagram is computed by: defining surface cells for different subcircuits in the semiconductor circuit, stipulating a uniform cell height for the surface cells, disposing the surface cells in one plane, and computing interconnect paths between the surface cells.
Such fabrication methods use “Place-and-Route” software programs which allow surface cells of different width, but of uniform height, to be disposed in a diagram corresponding to the surface of an integrated circuit which is to be fabricated, and to be connected to one another by interconnects, vias, etc. The uniform height of all the surface cells to be disposed is necessary for geometric reasons in order to be able to dispose surface cells of varying size in a space-saving manner without leaving unused interspaces between the surface cells remaining. Current computer programs make use of software libraries of standard cell sizes in which the electrical properties and the geometric dimensions of the standard cell and within the standard cell are prescribed for various microelectronic subcircuits, such as multiplexers, logic gates or flip-flops. All standardized surface cells in the software library have a uniform cell height.
Most of the subcircuits could also be accommodated in cells of a lesser height, but the uniform standard height is necessary for reasons of geometric arrangement. The standard height is prescribed by the largest subcircuits in a standard cell library. If a specific semiconductor circuit is to be planned, a computer program and the standard cell library can be used to compute the layout of the semiconductor circuit that is to be fabricated.
In contrast to this computer-aided manner of fabrication, a circuit layout can also be determined entirely by a layout that is manually optimized for each subcircuit or for each individual component. This results in surface area being saved on the semiconductor chip, albeit with serious cost drawbacks. Since the cost drawbacks usually predominate, use is made of the first technical method cited above, i.e. computer-aided design. The loss of surface area as compared with the manually optimized layout is more than compensated for as a result of the cost advantages of automatic layout calculation.